MMX is officially a meaningless initialism trademarked
unofficially, the initials have been variously explained as standing for MultiMedia eXtension
, Multiple Math eXtension
, or Matrix Math eXtension
, during one of its numerous court battles with Intel, produced marketing material from Intel indicating that MMX stood for “Matrix Math Extensions”. Since an initialism cannot be trademarked, this was an attempt to invalidate Intel’s trademark.
In 1997, Intel filed suit against AMD and Cyrix Corp. for misuse of its trademark MMX. AMD and Intel settled, with AMD acknowledging MMX as a trademark owned by Intel, and with Intel granting AMD rights to use the MMX trademark as a technology name, but not a processor name.
MMX defined eight registers
, known as MM0 through MM7 (henceforth referred to as MMn). To avoid compatibility problems with the context switch mechanisms in existing operating systems, these registers were aliases for the existing x87 FPU
stack registers (so no new registers needed to be saved or restored). Hence, anything that was done to the floating point stack would also affect the MMX registers and vice versa. However, unlike the FP stack, the MMn registers are directly addressable (random access).
Each of the MMn registers holds 64 bits (the mantissa
-part of a full 80-bit FPU register). The main usage of the MMX instruction set is based on the concept of packed data types, which means that instead of using the whole register for a single 64-bit integer, it is possible to process two 32-bit integers, four 16-bit integers, or eight 8-bit integers concurrently.
The mapping of the MMX registers onto the existing FPU registers made it somewhat difficult to work with floating point and SIMD data in the same application. To maximize performance, programmers often used the processor exclusively in one mode or the other, deferring the relatively slow switch between them as long as possible.
Because the FPU stack registers are 80 bits wide, the upper 16 bits of the stack registers go unused in MMX, and these bits are all set to ones, making them NaNs
or infinities in the floating point representation. This can be used to decide whether a particular register’s content is intended as floating point or SIMD data.
MMX provides only integer operations. When originally developed, for the Intel i860
, the use of integer math made sense (both 2D and 3D calculations required it), but as graphics cards that did much of this became common, integer SIMD
in the CPU became somewhat redundant for graphical applications. On the other hand, the saturation arithmetic
operations in MMX could significantly speed up some digital signal processing
, a competing x86 microprocessor vendor, enhanced Intel’s MMX with their own 3DNow!
instruction set. 3DNow is best known for adding single-precision (32-bit) floating-point support to the SIMD instruction-set, among other integer and more general enhancements.
Following MMX, Intel’s next major x86 extension was the SSE
, introduced with the Pentium-III family (roughly a year after AMD’s 3DNow! was introduced.)
SSE addressed the core shortcomings of MMX (inability to mix integer-SIMD ops with any floating-point ops) by creating a new 128-bit wide register file (XMM0–XMM7) and new SIMD instructions for it. Like 3DNow!, SSE focused exclusively on single-precision floating-point operations (32-bit); integer SIMD operations were still performed using the MMX register and instruction set. However, the new XMM register-file allowed SSE SIMD-operations to be freely mixed with either MMX or x87 FPU ops.
, introduced with the Pentium 4, further extended the x86 SIMD instruction set with integer (8/16/32 bit) and double-precision floating-point data support for the XMM register file. SSE2 also allowed the MMX opcodes to use XMM register operands, but ended this support with SSE4 (and recently with SSE4.2
, introduced in the Core microarchitecture
). However, since processor support for any SSE revision also implies support for MMX, the removal does not limit the data types usable by x86 SIMD.
Intel’s and Marvell
microprocessor core starting with PXA270 include an SIMD instruction set
extension to the ARM core called iwMMXt
whose functions are similar to those of the IA-32
MMX extension. iwMMXt stands for “Intel Wireless MMX Technology”. It provides arithmetic and logic operations on 64-bit integer numbers (the software may choose to instead perform two 32-bit, four 16-bit or eight 8-bit operations in a single instruction). The extension contains 16 data registers of 64-bits and eight control registers of 32-bits. All registers are accessed through standard ARM architecture
coprocessor mapping mechanism. iwMMXt occupies coprocessors 0 and 1 space, and some of its opcodes
clash with the opcodes of the earlier floating-point extension, FPA.
Later versions of Marvell
‘s ARM processors supports both WMMX (Wireless MMX) and WMMX2 (Wireless MMX2) support.